1. Field of the Invention
The present invention relates generally to a circuit for driving an integrated circuit (IC) output pad and more particularly to such a circuit which is configurable to effect different levels of output current drive. The present invention also relates generally to a method for making such a circuit.
2. Description of the Related Art
Output and input/output pads in integrated circuits are typically designed to provide a particular level of output current drive. When a different level of drive is needed, a new pad is designed. This approach requires a new pad design each time a different level of pad drive current is needed. In an effort to reduce pad design time, configurable circuits for driving an IC output pad were developed. One such circuit includes a plurality of field effect transistors (FETS) which are connected together in parallel. Typically there are two arrays of such FETs, one comprising an array of n-channel FETs connected together in parallel and the other comprising an array of p-channel FETs also connected together in parallel. One side of the n-channel FETs is connected to the pad and the other is grounded to provide sourcing drivers. One side of the p-channel FETs is also connected to the pad with the other side being connected to a power supply to provide sinking drivers.
Such a circuit for driving an IC output pad is embodied in a photolithographic mask formed by a prior art computer program. A circuit designer can then create additional artwork, utilizing the computer program, which adds connections to the circuit that tie off the gates of some of the FETs, thereby maintaining them in a permanently off condition, and that tie together the gates of the remaining FETs for driving the output pad responsive to a drive signal provided by the integrated circuit.
Tieing off the unused FETs directly to ground, in the case of n-channel FETs, or to a power supply, in the case of p-channel FETs, compromises electrostatic discharge (ESD) protection in that the tied-off FETs punch thru at different voltages from the FETs which are not tied off. This causes the group which punches thru first to absorb most of the energy of any ESD.
It is known in the art to tie off FETs by connecting the gates of the tied-off FETs to one side of another FET which is always in an on condition when voltage is applied to the IC. This improves ESD protection for the configurable circuit. However, when tied-off FETS are connected to one side of another FET, problems arise during IC testing before power is applied to the IC. Charge can build up on the gates of the tied-off FETs to a level which causes them to turn on thus causing leakage tests to fail.
In addition, such prior art circuits provide relatively coarse adjustment of how much drive current is provided. It would be desirable to provide finer resolution of the level of output current provided at the pad and to overcome problems associated with leakage testing of the above-described prior an circuit.